Interrupts and handling with single INTR pin

Interrupt

An interrupt is a signal (hardware) or an instruction (software) that makes the processor stop its present program temporarily, execute a special routine called the interrupt service routine (ISR) for the event, and then return to the program where it stopped.

Importance

• The CPU does not waste time polling devices continuously; it does useful work until a device needs service, so CPU utilisation is higher.
• Fast response to real-time events (power failure, keyboard press, timer).
• Allows slow devices and the fast CPU to work together efficiently.
• Allows software services (system calls) and error handling (divide error, overflow).
• Gives priority to important tasks and supports multitasking systems.

Handling many devices with the single INTR pin of the 8086

The 8086 has only one maskable interrupt input, INTR. To connect several devices, a programmable interrupt controller 8259A is placed between devices and the CPU.

 Dev0 --IR0 +---------+
 Dev1 --IR1 |         |--INT--> INTR (8086)
 ...        |  8259A  |<--INTA'-- INTA' (8086)
 Dev7 --IR7 |         |<->D7-D0<-> data bus
            +---------+

1. Up to 8 devices connect to IR0–IR7. When one or more raise their requests, the 8259A latches them in its IRR, checks the mask (IMR), and resolves priority.
2. It sends the signal INT to INTR of the 8086.
3. If IF = 1, the 8086 sends two INTA' pulses.
4. On the second INTA' the 8259A places the type number of the highest-priority request on D7–D0 (the base type set during initialisation plus the IR number).
5. The 8086 uses the type number to read the ISR address from the interrupt vector table, and serves that device.
6. The ISR gives an end-of-interrupt command (EOI) to the 8259A at the end.

More than 8 devices: up to 8 slave 8259A can be cascaded to one master, giving 64 interrupt levels on the single INTR pin. Other methods are polling and daisy-chaining, but the PIC is the standard method.