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Static differential relay for two-winding transformer

Short answer

A static differential relay for a two-winding transformer compares HV and LV CT currents after interposing CTs correct ratio and 30° phase shift. The bias circuit produces a restraint voltage proportional to through current; the spill circuit produces an operating voltage from the differential current. A 2nd-harmonic filter provides restraint during magnetizing inrush. An amplitude comparator checks if operating voltage exceeds K×restraint plus harmonic voltage; a high-set unit trips instantly for heavy internal faults. Output trips both HV and LV breakers.

Describe the circuit of static differential relay for protection of two winding transformer.

For a two-winding power transformer, a static differential relay compares the currents of the HV and LV CTs (after ratio and phase correction) and trips when the spill current exceeds a set percentage of the through current, with harmonic restraint to stay stable during magnetising inrush.

Circuit / block diagram (one phase)

 HV══CT1════[TRANSFORMER]════CT2══LV
      │      (Δ/Y)            │
 [Interposing CT,       [Interposing CT,
  ratio & 30° corr.]     ratio & 30° corr.]
      │ i1                 i2 │
      ├──[Bias rect.]──┬─[Bias rect.]──┤
      │                │ V_r           │
      └──────[Spill CT / summing]──────┘
                   │ i1 − i2
       ┌───────────┼─────────────┐
 [Fundamental] [2nd harmonic] [Unrestrained
  filter →       filter →      high-set
  rectifier]     rectifier]    level det.]
       │ V_o         │ V_h          │
 ┌─────▼─────────────▼──┐           │
 │ Comparator:          │           │
 │ V_o > K·V_r + V_h ?  │           │
 └─────────┬────────────┘           │
           └──────────[OR]──────────┘
                        │
              [Amplifier → thyristor]
                        │
                 Trip HV & LV CBs

Description of the circuit

  1. Main CTs and interposing CTs: main CTs on both sides; interposing (auxiliary) CTs match the current magnitudes (inverse of voltage ratio) and correct the 30° phase shift of Δ/Y connection. They also remove zero-sequence currents so that external earth faults do not cause tripping.
  2. Bias (restraint) circuit: i1 and i2 are rectified separately and summed across resistors to give V_r ∝ (|i1| + |i2|)/2 – the through current.
  3. Operating (spill) circuit: the difference current (i1 − i2) is passed through a filter tuned to 50 Hz and rectified to give V_o.
  4. Second-harmonic restraint: a 100 Hz filter extracts the 2nd harmonic in the spill current. During inrush (2nd harmonic > about 15–20% of fundamental) V_h becomes large and blocks tripping. A 5th-harmonic filter may be used for over-excitation restraint.
  5. Comparator: an amplitude comparator (op-amp) checks V_o > K·V_r + V_h. K is the bias slope (15–40%) which covers CT mismatch, tap-changer range and CT errors.
  6. Unrestrained (high-set) unit: for very heavy internal faults (spill > 8–10 × rating) it trips immediately without waiting for harmonic analysis, because CT saturation may produce harmonics.
  7. Output: OR gate, amplifier and thyristor/auxiliary relay trip both HV and LV circuit breakers.

Result: stable for load, external faults and inrush; fast (about 1–2 cycles) and sensitive for internal winding faults.

✓ Answer checked by Claude Opus 5.5 (high effort)

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