Sequence detector 101 using JK flip-flops

The machine watches the serial input X and makes Y = 1 when the last three bits received are 1, 0, 1.

A Mealy machine is used (output depends on the present state and the present input), and overlapping sequences are detected. Since the sequence has 3 bits, 3 states are needed, so 2 JK flip-flops ($Q_1Q_0$) are used, clocked on the positive edge. (A Moore machine would need 4 states.)

Step 1: States

Step 2: State diagram

 Main path (label = X/Y):
 A -1/0-> B -0/0-> C -1/1-> B
 Other transitions:
 A -0/0-> A    B -1/0-> B
 C -0/0-> A

Step 3: State assignment

Code 11 is unused and is treated as a don't care.

Step 4: Excitation table

JK excitation: 0→0: J=0, K=X; 0→1: J=1, K=X; 1→0: J=X, K=1; 1→1: J=X, K=0.

Step 5: K-maps (rows $Q_1$, columns $Q_0X$)

Step 6: Equations

$$\begin{aligned} &J_1 = Q_0\overline{X},\quad K_1 = 1 \\ &J_0 = X,\quad K_0 = \overline{X} \\ &Y = Q_1X \end{aligned}$$

Step 7: Logic diagram

   +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1
   | FF0 |       | FF1 |
K0>|K    |    K1>|K    |
   +--^--+       +--^--+
      |             |
CLK---+-------------+
X = serial input, common to the gates
J1 = Q0.X'   K1 = 1
J0 = X   K0 = X'
Y = Q1.X

The gates for each flip-flop input are built from the equations; the output gate gives Y directly (Mealy output).

Unused state 11: with the equations above, from 11 the machine goes to 00 when X = 0 and to 01 when X = 1, so it enters the valid states after one clock. Since Y can be 1 from state 11 for one clock, the flip-flops should be cleared to 00 at power-on (reset).

Check with an input stream

Y = 1 appears exactly on the clock in which the last bit of 101 arrives; overlapping sequences are also detected.