Three consecutive zeros detector using SR

Output y of the question is written Z (y = Z). With overlapping, every 0 after two 0s gives Z = 1.

A Mealy machine is used (output depends on present state and input), so fewer states are needed. Overlapping sequences are allowed: after a detection the machine keeps the useful tail of the input. One input X and one output Z; Z = 1 in the clock period in which the last bit of 000 arrives. Flip-flops: S-R.

States (what has been received so far):

• A: reset / last bit 1
• B: one 0 received
• C: two or more consecutive 0s

State diagram (Mealy)

Arc label = input/output

 A --0/0--> B --0/0--> C --0/1--> C

 A --1/0--> A  (self loop)
 B --1/0--> A
 C --1/0--> A

State table

State assignment

A = 00, B = 01, C = 10 (flip-flop outputs $Q_1 Q_0$). The unused code 11 is taken as don't care (x) in all K-maps. The flip-flops are cleared to 00 at power-on (start state). Checking the final equations, from 11 the machine goes to a valid state on the next clock (X=0 goes to C, X=1 goes to A), so it is self-starting.

Excitation table of S-R flip-flop

Transition and excitation table

K-maps and simplified equations

S1          X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       1    0
Q1Q0=11       x    x
Q1Q0=10       x    0

R1          X=0  X=1
Q1Q0=00       x    x
Q1Q0=01       0    x
Q1Q0=11       x    x
Q1Q0=10       0    1

S0          X=0  X=1
Q1Q0=00       1    0
Q1Q0=01       0    0
Q1Q0=11       x    x
Q1Q0=10       0    0

R0          X=0  X=1
Q1Q0=00       0    x
Q1Q0=01       1    1
Q1Q0=11       x    x
Q1Q0=10       x    x

Z           X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       0    0
Q1Q0=11       x    x
Q1Q0=10       1    0

$$\begin{aligned} S_1 &= Q_0 X' \\ R_1 &= X \\ S_0 &= Q_1' Q_0' X' \\ R_0 &= Q_0 \\ Z &= Q_1 X' \end{aligned}$$

Logic diagram

           +-------------+     +----------+
 X  ------>| next-state  |---->| FF1, FF0 |--+--> Q1, Q0
    +----->| logic       |     |  (CLK)   |  |
    |      +-------------+     +----------+  |
    +-------------------<--------------------+
    |      +-------------+
    +----->| output      |----> Z
 X  ------>| logic       |
           +-------------+

Gates needed (two S-R flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates):

• $S_1$: a 2-input AND for $Q_0 X'$.
• $R_1$: direct line $X$.
• $S_0$: a 3-input AND for $Q_1' Q_0' X'$.
• $R_0$: direct line $Q_0$.
• $Z$: a 2-input AND for $Q_1 X'$.

Check: input X = 1000010 gives Z = 0001100; Z = 1 at bits 4 and 5.