Problems in asynchronous sequential design

An asynchronous sequential circuit has no clock: its state (held in feedback loops through gate delays) changes as soon as an input changes. This makes it fast, but the design has several problems that clocked circuits avoid.

1. Races

A race happens when two or more state variables must change in one transition. Due to unequal delays they do not change together, so the circuit passes through an intermediate state.

• Non-critical race: the circuit still reaches the correct final state whatever order the variables change in.
• Critical race: the final stable state depends on which variable changes first, so the circuit may settle in a wrong state.

Example: state $y_1 y_2$ must go from 00 to 11. If $y_1$ changes first the circuit passes 10; if $y_2$ first, it passes 01. If, for the present input, 01 is a stable state, the circuit stops at 01 instead of 11 — a critical race.

  00 ---> 11   intended
  00 ---> 10 ---> 11   (y1 first, OK)
  00 ---> 01 (stable) stuck  (y2 first, error)

Remedy: choose a race-free state assignment (adjacent codes differing in one bit), add extra states, or use a one-hot code.

2. Cycles

The circuit may go through a sequence of unstable states before reaching a stable one. If no stable state exists in that column, it keeps oscillating (an unending cycle) between states.

3. Hazards

Unequal gate delays give momentary wrong outputs (glitches):

• Static-1 hazard: output should stay 1 but drops to 0 briefly, e.g. $F = AB + A'C$ when A changes with B = C = 1. Fixed by adding the consensus term $BC$.
• Static-0 hazard: output should stay 0 but rises to 1 briefly. Dynamic hazard: output should change once but changes several times (e.g. 1 → 0 → 1 → 0) before settling.
• Essential hazard: caused by an input change reaching different parts of the circuit at different times; removed by adding delay in the feedback.

Because the feedback loops carry these glitches back to the inputs, a hazard can push the circuit into a wrong stable state.

4. Other restrictions

• Fundamental mode: only one input may change at a time, and only after the circuit is stable.
• Analysis and design are harder (flow table, merging of rows, state assignment), and the circuit is sensitive to temperature and delay variations.