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Transformer on load and no load, phasor diagrams

Short answer

At no load, primary draws a small lagging exciting current I0 with core-loss and magnetizing components. On resistive load, I2 is in phase with V2, and E2 > V2 giving a slight voltage drop. On capacitive load, I2 leads V2; the reactance drop partially opposes V2, so E2 may be smaller than V2, causing a voltage rise (negative regulation).

Explain the transformer on load and no load with the phasor diagram of resistive and capacitive load.

A practical transformer has winding resistances R1,R2R_1, R_2, leakage reactances X1,X2X_1, X_2 and a core that draws an exciting current I0I_0.

No-load operation

The secondary is open (I2=0I_2 = 0). The primary draws only I0I_0, which has two components:

I0=Ic+Iμ,Ic=I0cos⁡ϕ0 (core loss),Iμ=I0sin⁡ϕ0 (magnetising)I_0 = I_c + I_\mu,\qquad I_c = I_0\cos\phi_0\ (\text{core loss}),\qquad I_\mu = I_0\sin\phi_0\ (\text{magnetising})
              V1 (= -E1 approx)
               ^
               |
          Ic   |      . I0
     (along V1)|    .
               |  .     phi0 = angle between V1 and I0
               |.          (about 75-80 deg)
               +-------------------> Im, flux phi
               |
               v
             E1, E2 (lag phi by 90 deg)
  • IcI_c is in phase with V1V_1 and supplies the core loss.
  • IμI_\mu lags V1V_1 by 90°, and the flux ϕ\phi is in phase with IμI_\mu.
  • E1E_1 and E2E_2 lag ϕ\phi by 90°, so E1E_1 is opposite to V1V_1.
  • I0I_0 is small (2 to 5% of full-load current) and lags V1V_1 by ϕ0\phi_0, so the no-load power factor is low (about 0.1 to 0.25).

On load

The secondary current I2I_2 flows, and the primary takes the additional load component I1′=I2/aI_1' = I_2/a, so I1=I0+I1′I_1 = I_0 + I_1' (phasor sum). The voltage equations are

V1=−E1+I1(R1+jX1),V2=E2−I2(R2+jX2)V_1 = -E_1 + I_1(R_1 + jX_1),\qquad V_2 = E_2 - I_2(R_2 + jX_2)

Resistive load. I2I_2 is in phase with V2V_2. E2E_2 is found by adding to V2V_2 the drop I2R2I_2R_2 (in phase with I2I_2) and I2X2I_2X_2 (90° ahead of I2I_2). So E2>V2E_2 > V_2 and the terminal voltage falls on load. I1′I_1' is in phase with −I2-I_2 (it is drawn in phase with −E1-E_1), and I1I_1 is close to I1′I_1'. The primary power factor is nearly unity.

  Resistive load (phasors referred to secondary)

          E2
         /|
        / | I2X2
       /  |
      /___|______
      V2  I2R2    I2 along V2

Capacitive load. I2I_2 leads V2V_2 by ϕ2\phi_2. The drops I2R2I_2R_2 and I2X2I_2X_2 are drawn along I2I_2 and 90° ahead of it. Because I2I_2 is now ahead of V2V_2, the drop I2X2I_2X_2 points partly opposite to V2V_2, and E2E_2 becomes smaller than V2V_2: approximately E2≈V2+I2R2cos⁡ϕ2−I2X2sin⁡ϕ2E_2 \approx V_2 + I_2R_2\cos\phi_2 - I_2X_2\sin\phi_2. So the secondary terminal voltage rises on load (negative regulation) when the leading power factor is low enough.

  Capacitive load (V2 as reference, I2 leads V2 by phi2)

               E2 tip <-----------+
                 .'      I2X2     /
              .'                 / I2R2 (along I2)
   O ----------------------------+ V2
      E2 runs from O to E2 tip and is shorter than V2

In each case, I1I_1 is obtained as I0+I1′I_0 + I_1', and V1=−E1+I1(R1+jX1)V_1 = -E_1 + I_1(R_1 + jX_1) completes the primary diagram. For the capacitive load I1′I_1' leads −E1-E_1, so the primary power factor is leading when the load current is large compared with I0I_0.

✓ Answer checked by Claude Opus 5.5 (high effort)

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