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Machine from 3-state diagram using SR

Short answer

Assign states X=00, Y=01, Z=10. Output F=1 only in Z with W=1 (three consecutive 1s). S1=Q0 W, R1=W', S0=Q1' Q0' W, R0=Q0, F=Q1 W. Two S-R flip-flops.

Design a synchronous sequential machine from the state diagram given below. Use S-R Flip-Flop. [Figure: state diagram with three states X, Y, Z, edges labelled input/output: X→X on 0/0; X→Y on 1/0; Y→X on 0/0; Y→Z on 1/0; Z→Z on 1/1; Z→X on 0/0]

The state diagram is a Mealy diagram with 3 states. To avoid confusion with the state names X, Y, Z, the input is called W and the output F. From the diagram, F = 1 only when the machine is in Z and W = 1, i.e. the machine detects three or more consecutive 1s. Flip-flops: S-R.

State diagram (given)

Arc label = input/output

 X --1/0--> Y --1/0--> Z --1/1--> Z

 X --0/0--> X  (self loop)
 Y --0/0--> X
 Z --0/0--> X

State table

Present stateNext, W=0Next, W=1F (W=0)F (W=1)
XXY00
YXZ00
ZXZ01

State assignment

X = 00, Y = 01, Z = 10 (flip-flop outputs Q1Q0Q_1 Q_0). The unused code 11 is taken as don't care (x) in all K-maps. The flip-flops are cleared to 00 at power-on (start state). Checking the final equations, from 11 the machine goes to a valid state on the next clock (W=0 goes to X, W=1 goes to Z), so it is self-starting.

Excitation table of S-R flip-flop

QQ+SR
000x
0110
1001
11x0

Transition and excitation table

Q1 Q0WQ1+ Q0+S1R1S0R0F
0 000 00x0x0
0 010 10x100
0 100 00x010
0 111 010010
1 000 0010x0
1 011 0x00x1

K-maps and simplified equations

S1          W=0  W=1
Q1Q0=00       0    0
Q1Q0=01       0    1
Q1Q0=11       x    x
Q1Q0=10       0    x

R1          W=0  W=1
Q1Q0=00       x    x
Q1Q0=01       x    0
Q1Q0=11       x    x
Q1Q0=10       1    0

S0          W=0  W=1
Q1Q0=00       0    1
Q1Q0=01       0    0
Q1Q0=11       x    x
Q1Q0=10       0    0

R0          W=0  W=1
Q1Q0=00       x    0
Q1Q0=01       1    1
Q1Q0=11       x    x
Q1Q0=10       x    x

F           W=0  W=1
Q1Q0=00       0    0
Q1Q0=01       0    0
Q1Q0=11       x    x
Q1Q0=10       0    1
S1=Q0WR1=W′S0=Q1′Q0′WR0=Q0F=Q1W\begin{aligned} S_1 &= Q_0 W \\ R_1 &= W' \\ S_0 &= Q_1' Q_0' W \\ R_0 &= Q_0 \\ F &= Q_1 W \end{aligned}

Logic diagram

           +-------------+     +----------+
 W  ------>| next-state  |---->| FF1, FF0 |--+--> Q1, Q0
    +----->| logic       |     |  (CLK)   |  |
    |      +-------------+     +----------+  |
    +-------------------<--------------------+
    |      +-------------+
    +----->| output      |----> F
 W  ------>| logic       |
           +-------------+

Gates needed (two S-R flip-flops with a common clock; complements are taken from the Q′Q' outputs or NOT gates):

  • S1S_1: a 2-input AND for Q0WQ_0 W.
  • R1R_1: direct line W′W'.
  • S0S_0: a 3-input AND for Q1′Q0′WQ_1' Q_0' W.
  • R0R_0: direct line Q0Q_0.
  • FF: a 2-input AND for Q1WQ_1 W.

Check: input W = 0111101 gives F = 0001100 — F = 1 at the 3rd and 4th consecutive 1, as the diagram requires (Z → Z on 1/1).

✓ Answer checked by Claude Opus 5.5 (high effort)

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