Switch bounce; negative edge RS flip-flop

Eliminating switch contact bounce

When a mechanical switch is closed or opened, its contacts bounce several times for a few milliseconds, so a digital circuit sees many pulses instead of one clean transition.

Method 1: SR (NAND) latch debouncer using an SPDT switch:

 +5V-[R1]-+-------S'-->+--------+
          |            | NAND   |--> Q (clean)
     A  o-+            | SR     |
         \             | latch  |--> Q'
  GND --o  (arm)       |        |
     B  o-+            |        |
          |            |        |
 +5V-[R2]-+-------R'-->+--------+

• When the switch moves from A to B, the first touch at B resets the latch.
• Bounces at B only make R' go 1, 0, 1, ...; with S' = 1 and R' = 1 the latch holds its state, so the output stays clean.
• The output changes only once, at the first contact.

Method 2: an RC filter followed by a Schmitt-trigger inverter (e.g. 74HC14); the capacitor smooths the bounces and the hysteresis gives one clean edge. Method 3: software delay (about 10–20 ms) in microcontrollers.

Negative edge-triggered RS flip-flop

It changes state only at the falling edge of the clock. An edge detector makes a very narrow pulse CLK* when CLK goes from 1 to 0, and the steering gates G1 and G2 are enabled only during this pulse. Symbol: triangle with a bubble at CLK.

 CLK --+--->[ NOT ]----------->+-----+
       |                       | AND |---> CLK*
       +--->[ delay dt ]------>+-----+
 CLK* = CLK' . CLK(delayed): a narrow pulse
 at every falling edge of CLK

          +------+  S*  +------+
 S -------| NAND |----->| NAND |-----> Q
 CLK* ----|  G1  |  Q'->|  G3  |
          +------+      +------+
          +------+  R*  +------+
 R -------| NAND |----->| NAND |-----> Q'
 CLK* ----|  G2  |  Q-->|  G4  |
          +------+      +------+
 G3 and G4 form a cross-coupled NAND latch.

Excitation table

Characteristic equation: $Q_{n+1} = S + R'Q_n$ with $SR = 0$.