Race around condition; JK to SR conversion

Race-around condition

In a level-triggered J-K flip-flop with J = K = 1, the output toggles once after one propagation delay $\Delta t$. If the clock is still high, the new output feeds back to the input gates and makes it toggle again, and again, as long as CLK = 1. At the end of the pulse the output state is unpredictable. This repeated toggling during one clock pulse is the race-around condition. It happens when the clock pulse width $t_p > \Delta t$.

 CLK  ___|‾‾‾‾‾‾‾‾‾‾‾‾|___
 Q    ___|‾‾|__|‾‾|__|‾‾‾   (J = K = 1)

It is avoided by keeping $t_p < \Delta t < T$, by edge triggering, or by a master-slave J-K flip-flop.

Limitations of S-R flip-flop

• S = R = 1 is a forbidden input: both outputs become equal (not complements).
• If S and R go from 1,1 to 0,0 together, the final state is indeterminate (depends on gate speeds).
• So the circuit using it must always prevent S = R = 1; it cannot toggle and is not directly useful for counters.

Converting J-K flip-flop to S-R flip-flop

J-K excitation table:

Conversion table (Q+ from the S-R table; S = R = 1 is not allowed, so those rows are don't-cares):

K-maps:

K-map for J
Q\SR   00  01  11  10
 0      0   0   x   1
 1      x   x   x   x

K-map for K
Q\SR   00  01  11  10
 0      x   x   x   x
 1      0   1   x   0

$$J = S, \qquad K = R$$

          +---------+
 S -------| J     Q |--- Q
 CLK -----|>  JK    |
 R -------| K    Q' |--- Q'
          +---------+

A J-K flip-flop works as an S-R flip-flop with S connected to J and R connected to K directly; no extra gates are needed. (For S = R = 1 it toggles instead of giving an invalid output, but that input is still not used for S-R operation.)